Nvidia still controls roughly 80% of the AI accelerator market, and its data center chips remain the default choice for anyone building or training a large language model. But four of its biggest customers, Google, Amazon, Microsoft, and Meta, are also its most determined competitors. Each has spent years building its own AI chips, and in 2026 those chips are no longer experimental side projects. They are running production workloads at a scale that would have been unthinkable three years ago.
The question that matters for anyone buying compute isn’t whether Nvidia is dominant. It clearly is. The question is whether that dominance is built on hardware that happens to be the best available, or on something stickier: software that took two decades to build and would take years to replace. That distinction, hardware versus software lock-in, is where the real competitive story sits in 2026.
What the CUDA moat actually is
CUDA gets described as Nvidia’s competitive advantage so often that the phrase has become a cliché. What it actually means is more specific. CUDA is not one product. It is a stack of libraries, compilers, and tools built up over more than 20 years: cuDNN, cuBLAS, NCCL, TensorRT-LLM, and the wider layer of open-source projects built on top of it, including FlashAttention, vLLM, and SGLang. Nearly every serious optimization technique used in production LLM inference today, continuous batching, paged attention, speculative decoding, FP8 quantization kernels, was built and tuned specifically for CUDA.
This is easy to underestimate if you’ve never had to build on it. It’s not that Nvidia wrote all of this software itself, though it wrote a large chunk of it. It’s that thousands of outside engineers, at universities, at startups, at every major AI lab, spent years building and testing tools on top of CUDA because that’s what everyone else was already using. That’s a feedback loop that’s genuinely hard to break from the outside, and it’s a big part of why a chip that matches Nvidia’s specs on paper still doesn’t automatically win a workload.
That’s the part competitors can’t just copy by shipping faster silicon. A chip is a chip. You can match FLOPs and memory bandwidth on a spec sheet in a generation or two, and several companies already have. But a decade of accumulated software tooling, tested across thousands of production deployments, isn’t something you replicate with a good product launch.
Here’s the more precise way to think about it: the CUDA moat isn’t really a wall that keeps competitors out. It’s a toll. Any team currently running vLLM, SGLang, or TensorRT-LLM in production faces real engineering cost to move to a non-CUDA chip. Migrating to AWS Trainium means rewriting for the Neuron SDK. Migrating to Google’s TPUs means adopting JAX and MaxText. Migrating to Microsoft’s Maia or Meta’s MTIA isn’t really an option at all for outside developers, because those chips are captive to their parent company’s infrastructure. The cost isn’t infinite. It’s weeks to months of engineering work, with no guarantee everything ports cleanly. For a large team, that’s a real decision point. For a small one, it’s often a dealbreaker.
The four companies building their way around Nvidia
Google has the most mature program by a wide margin. Its TPU line goes back roughly a decade, and the seventh-generation chip, codenamed Ironwood, has been in preview since late 2025 after being announced in April of that year. It’s co-developed with Broadcom and MediaTek and built on TSMC’s N3P process. Google reportedly runs more than 75% of Gemini workloads on TPUs internally, and the company has projected 4.3 million TPU shipments in 2026. That’s not a hedge against Nvidia anymore. That’s a primary compute strategy.
Amazon’s approach looks similar but younger. Trainium3, AWS’s first chip built on a 3-nanometer process, went generally available at re:Invent in December 2025, delivering roughly 2.52 PFLOPs of FP8 compute and 144GB of HBM3e memory per chip. AWS has published internal benchmarks claiming competitive cost-per-token against Nvidia GPUs for dense transformer inference, though it’s worth flagging that these are AWS’s own figures, not independently reproduced ones, and they apply specifically to models ported to the Neuron SDK. What’s more interesting is what Amazon is reportedly considering next. Bloomberg reported in mid-June 2026 that Amazon is in early talks to sell Trainium chips directly to outside data centers, a break from the AWS-only distribution model the company has stuck to since Trainium launched. Those are reportedly still talks, not signed deals, but the direction is telling.
Microsoft’s Maia 200 arrived in January 2026, an inference-focused accelerator built on TSMC’s 3-nanometer node with 216GB of HBM3e memory. It’s already in mass production, serving Microsoft 365 Copilot workloads, and there were unconfirmed reports as of May 2026 that Anthropic was in talks to become an external customer. Microsoft paired the chip with its own Cobalt 100 Arm-based CPU for general cloud workloads, which isn’t an AI chip in itself but frees up budget and reduces dependence on Intel and AMD for infrastructure that used to run on their silicon by default.
Meta’s MTIA program is smaller in deployed volume, an estimated 180,000 units in 2026 compared to roughly 900,000 TPUs and 600,000 Trainium chips, but it follows the same logic: run internal recommendation and ranking workloads on custom silicon, save the Nvidia GPU budget for training the largest models.
Then there’s AMD, which is a genuinely different case because it’s not a hyperscaler building for itself. It’s selling a general-purpose GPU roadmap in direct competition with Nvidia, the way it always has. The MI350X already matches Nvidia’s B200 on FP8 TFLOPS in spec comparisons, and AMD’s MI400 series is landing in the second half of 2026 on TSMC’s 2-nanometer process, backed by a multi-gigawatt compute deal with OpenAI. AMD’s Helios rack configuration packs 72 of the newer MI455X GPUs together. On paper, AMD is closer to Nvidia than it’s been in years. In market share, it’s still sitting at roughly 5 to 7% against Nvidia’s 80%, according to analyst estimates from April 2026. Software, again, is most of the gap. AMD’s ROCm 7 platform is reportedly within 10 to 30% of CUDA performance for most workloads now, which sounds close until you remember that a 20% performance gap at data center scale is millions of dollars.
Where the moat is actually cracking
The honest answer is: mostly at the edges, not the center. Industry trackers estimate combined hyperscaler custom silicon deployment at roughly 1.9 million accelerators in 2026, up sharply from prior years, and that number is gradually eating into Nvidia’s share of total data center accelerator deployment. But the erosion isn’t happening evenly across workload types.
Inference is where custom silicon is making the most headway. It’s a narrower, more predictable computational problem than training, which makes it easier to optimize for on purpose-built hardware without needing CUDA’s flexibility. Training, especially of frontier-scale models, is a different story. Nvidia’s GPUs, and the NVLink interconnect that lets them scale across thousands of chips as one coherent system, remain the default for anyone pushing the largest model runs. That said, the line is blurring. AWS’s Trainium3 is reportedly already being used by frontier labs, including Anthropic and OpenAI according to some reporting, for both training and inference, not just inference. That’s a meaningful shift from a year ago, when custom silicon was treated almost exclusively as an inference-cost play.
There’s also a revenue nuance that’s easy to miss if you only look at unit counts. Custom silicon tends to be cheaper per chip than premium Nvidia SKUs, so even as the number of non-Nvidia accelerators deployed climbs, the dollar-share shift is smaller than the unit-share shift. Nvidia is still capturing the majority of total AI accelerator revenue, even in a year where its unit share is visibly narrowing. It’s a bit like watching a company lose market share on paper while its bank account tells a calmer story.
One more data point worth including here, because it doesn’t get much attention outside chip-industry circles: Broadcom, which designs the custom silicon for Google and reportedly others, posted AI ASIC revenue north of $20 billion in fiscal 2025 with a $73 billion backlog. That backlog number matters more than almost any other figure in this piece. It tells you hyperscalers aren’t dabbling. They’ve placed years of orders.
What Nvidia still has that nobody else does
Three things, roughly. First, the software stack described above, which remains the deepest and most tested in the industry by a wide margin. Second, training dominance at the frontier, where NVLink’s multi-node scaling and the raw compute of chips like the B300 Blackwell Ultra, rated at 288GB of HBM3e and 15 PFLOPs of dense FP4 performance, are genuinely difficult to match today. Third, and this one gets underrated, reach. Nvidia hardware runs in every cloud, every research lab, every on-prem deployment, and every startup’s rented GPU cluster. Custom chips are locked to their parent company’s infrastructure. A university lab or a small AI startup can’t buy a TPU the way it can rent an H100. That changes the addressable market in Nvidia’s favor even before performance enters the conversation.
Put those three together and you get something closer to a network effect than a hardware lead. Every new optimization technique published in a research paper gets a CUDA implementation first, often within days, because that’s where the reviewers and the reproducibility crowd are. Every new open-source inference framework targets CUDA first for the same reason. Nvidia isn’t just selling chips faster than competitors can copy them. It’s sitting at the center of where the AI research community already works, which is a much harder position to dislodge.
Jensen Huang has been fairly consistent in public comments that the software ecosystem, not the silicon, is what he considers the company’s real defense. Whether that holds depends less on Nvidia’s next chip launch and more on how quickly tools like OpenAI’s Triton compiler and PyTorch’s torch.compile abstraction layer mature. Both are explicitly trying to let developers write code once and run it on whatever hardware is underneath, CUDA or otherwise. If that abstraction layer gets good enough, it chips away at exactly the lock-in that makes CUDA valuable in the first place. It’s not there yet. Full parity, by most estimates in this space, is still years away. But it’s the one long-term threat that isn’t really about anyone’s chip at all.
The cost math nobody puts on a slide
Here’s the part that gets skipped in most coverage of this fight: the CUDA moat isn’t just an engineering cost, it’s an ongoing operational cost too, and that’s where custom silicon makes its strongest case. Running a fleet of Nvidia GPUs at scale means using Nvidia’s own monitoring and diagnostics tools, DCGM and NVSMI, over standard InfiniBand or Ethernet networking that most data center teams already know how to run. Custom ASICs don’t work that way. Google TPUs, AWS Trainium, and Microsoft Maia each ship with their own proprietary monitoring and orchestration stack, and each uses its own interconnect, an optical mesh here, AWS’s EFA fabric there, a custom Azure setup somewhere else. Operations teams supporting those chips need training and tooling that’s completely different from what they’d use on Nvidia hardware.
That sounds like a minor detail until you picture the actual data center floor. A single facility running a mixed fleet might have air-cooled legacy Nvidia servers, direct liquid-cooled custom ASICs, and immersion-cooled Nvidia NVL systems all in the same building, each with its own maintenance procedure and its own failure recovery playbook. That’s not a hypothetical. It’s already how some of the largest hyperscaler facilities operate today. For a company Amazon’s or Google’s size, that complexity is a cost worth absorbing because the chips are cheaper per unit and they’re building at a scale where even small per-chip savings add up to billions. For a smaller operator, that same complexity is usually a reason to just stay on Nvidia and pay the premium. Simplicity has a price, and plenty of teams are happy to pay it.
What frontier labs are actually doing with their compute budgets
The clearest signal of where this is heading isn’t in a press release, it’s in what the AI labs building the biggest models are quietly choosing to run their workloads on. For most of the last three years, the assumption was straightforward: frontier labs train on Nvidia, full stop, because nothing else can handle a run at that scale without falling over. That assumption doesn’t hold as cleanly anymore. Reporting through mid-2026 suggests AWS’s Trainium3 chips are being used by frontier labs, including names as prominent as Anthropic and OpenAI, for training work as well as inference, not just the cheaper inference workloads custom silicon has traditionally been steered toward. Some of that reporting remains unconfirmed at the individual-deal level, and companies in this space are understandably tight-lipped about exactly which chips power which models. But the direction of travel is hard to miss.
AMD is playing a similar game from a different angle. Its multi-gigawatt compute deal with OpenAI, tied to the MI400 series launching in the back half of 2026, is a bet that a general-purpose GPU roadmap can still win real training business away from Nvidia if the price and performance gap closes far enough. Whether that bet pays off depends almost entirely on how good AMD’s ROCm software gets over the next year or two, since the MI400’s raw specs are already competitive. It’s the software, again, that decides who actually wins the workload, not the chip alone.
Why this matters beyond the spec sheets
For a company or developer deciding what to build on, the practical takeaway isn’t “Nvidia is being overtaken.” It isn’t. The takeaway is closer to what a few infrastructure analysts have started saying this year: allocate Nvidia budget toward the workloads where CUDA’s flexibility is genuinely irreplaceable, mainly large-scale training and anything CUDA-dependent through third-party frameworks, and treat high-volume, predictable inference as an area where custom silicon or AMD’s improving ROCm stack is worth evaluating on cost.
That’s a more complicated answer than the market-share headline suggests, and probably a more honest one. Nvidia’s August 26 earnings call, covering its second fiscal quarter of 2027, will likely draw another round of stock commentary either way, since the market has grown strangely numb to strong Nvidia quarters over the past year. Even a clean beat-and-raise result hasn’t been enough to move the stock much for several quarters running now, which says more about how priced-in Nvidia’s dominance already is than it does about the company’s actual performance.
But the actual competitive story isn’t going to be settled in a single earnings report, and it’s probably a mistake to keep waiting for one moment that settles it. It’s going to be settled gradually, workload by workload, as more teams decide whether the CUDA toll is worth paying. For the biggest hyperscalers, with in-house chip programs and engineering teams built specifically to absorb that migration cost, the answer is increasingly no for a growing slice of their internal workloads. For almost everyone else, renting an H100 or a B200 with no lock-in and no new tooling to learn is still the easier decision by a wide margin. Both of those things can be true about Nvidia at the same time, and probably will be for a while yet.